`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:25:41 04/05/2011 
// Design Name: 
// Module Name:    DataMem 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DataMem(clk, addr, writeData, MemWrite, MemRead, readData, reset);
    input clk;
	 input [15:0] addr;
    input [15:0] writeData;
    input MemWrite;
    input MemRead;
	 input reset;
    output [15:0] readData;
	 
	 reg [15:0] readData;
	 reg [15:0] dataMem [0:31]; //Temporary. There is absolutely no need for a memory this deep. We'll need to cut down.
	 
	 //The timing of this can get tricky. At the clock edge, the previous contents of EX/MEM would have propagated
	 //through the memory so they would correctly update to MEM/WB. This also time for the write address/MemWrite 
	 //lines to stabilize. Only do writes on this clock edge.
	 always @ (posedge clk)
		if (MemWrite) dataMem[addr] <= writeData;
		
	 //Read whenever	
	 always @ (addr or MemRead)
		if (MemRead) readData <= dataMem[addr];

/*always @ (posedge reset)
	 begin
		//32 memories should be sufficient
		dataMem[16'd0] <= 0;
		dataMem[16'd1] <= 0;
		dataMem[16'd2] <= 0;
		dataMem[16'd3] <= 0;
		dataMem[16'd4] <= 0;
		dataMem[16'd5] <= 0;
		dataMem[16'd6] <= 0;
		dataMem[16'd7] <= 0;
		dataMem[16'd8] <= 0;
		dataMem[16'd9] <= 0;
		dataMem[16'd10] <= 0;
		dataMem[16'd11] <= 0;
		dataMem[16'd12] <= 0;
		dataMem[16'd13] <= 0;
		dataMem[16'd14] <= 0;
		dataMem[16'd15] <= 0;
		dataMem[16'd16] <= 0;
		dataMem[16'd17] <= 0;
		dataMem[16'd18] <= 0;
		dataMem[16'd19] <= 0;
		dataMem[16'd20] <= 0;
		dataMem[16'd21] <= 0;
		dataMem[16'd22] <= 0;
		dataMem[16'd23] <= 0;
		dataMem[16'd24] <= 0;
		dataMem[16'd25] <= 0;
		dataMem[16'd26] <= 0;
		dataMem[16'd27] <= 0;
		dataMem[16'd28] <= 0;
		dataMem[16'd29] <= 0;
		dataMem[16'd30] <= 0;
		dataMem[16'd31] <= 0;
	 end
*/
endmodule
